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cy2308 3.3 v zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07146 rev. *o revised march 13, 2014 3.3 v zero delay buffer features zero input-output propagation delay, adjustable by capacitive load on fbk input multiple configurations, see available cy2308 configurations on page 4 for more details multiple low skew outputs two banks of four outputs, three-stateable by two select inputs 10 mhz to 133 mhz operating range 75 ps typical cycle-to-cycle jitter (15 pf, 66 mhz) space saving 16-pin 150 mil soic package or 16-pin tssop 3.3 v operation industrial temperature available functional description the cy2308 is a 3.3 v zero delay buffer designed to distribute high speed clocks in pc, workstation, datacom, telecom, and other high performance applications. the part has an on-chip pll that locks to an input clock presented on the ref pin. t he pll feedback is driven from external fbk pin, so user has flexibility to choose any one of the outputs as feedback input and connect it to fbk pin. the input-to-output skew is less than 250 ps and output-to-output skew is less than 200 ps. the cy2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table select input decoding on page 3. if all output clocks are not required, bank b is three-stated. the input clock is directly applied to the output for chip and system testing purpos es by the select inputs. the cy2308 pll enters a power down state when there are no rising edges on the ref input. in this mode, all outputs are three-stated and the pll is turned off resulting in less than 25 ? a of current draw. the pll shuts down in two additional cases as shown in the table select input decoding on page 3 . multiple cy2308 devices acce pt the same input clock and distribute it in a system. in this case, the skew between the outputs of two devices is less than 700 ps. the cy2308 is available in five different configurations as shown in the table available cy2308 configurations on page 4 . the cy2308-1 is the base part where the output frequencies equal the reference if there is no counter in the feedback path. the cy2308-1h is the high drive version of the -1 and rise and fall times on this devi ce are much faster. the cy2308-2 enables the user to obtain 2x and 1x frequencies on each output bank. the exact configuration and output frequencies depend on the user?s selection of out put that drives the feedback pin. the cy2308-3 enables the user to obtain 4x and 2x frequencies on the outputs. the cy2308-4 enables the user to obtain 2x clocks on all outputs. thus, the part is extrem ely versatile and is used in a variety of applications. the cy2308-5h is a high drive version with ref/2 on both banks. ref clka1 clka2 clka3 clka4 fbk pll mux select input decoding s2 s1 clkb1 clkb2 clkb3 clkb4 /2 extra divider (?2, ?3) /2 extra divider (?3, ?4) extra divider (?5h) /2 logic block diagram
cy2308 document number: 38-07146 rev. *o page 2 of 20 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 select input decoding ...................................................... 3 available cy2308 configurations ................................... 4 zero delay and skew control .......................................... 4 maximum ratings ............................................................. 5 operating conditions for commercial temperature devices ............................ 5 electrical characteristics for commercial temperature devices ............................ 5 switching characteristics for commercial temperature devices ............................ 6 operating conditions for industrial temperature devices ................................ 7 electrical characteristics for industrial temperature devices ................................ 7 switching characteristics for industrial temperature devices ................................ 8 switching waveforms ...................................................... 9 typical duty cycle and idd tren ds .............................. 10 typical duty cycle and idd trends .............................. 11 test circuits .................................................................... 12 ordering information ...................................................... 13 ordering code definitions ..... .................................... 14 package diagrams .......................................................... 15 acronyms ........................................................................ 16 document conventions ................................................. 16 units of measure ....................................................... 16 errata ............................................................................... 17 part numbers affected .............................................. 17 cy2308 errata summary ........ ............... ........... ........ 17 cy2308 qualification status ............... .............. ........ 17 document history page ................................................. 19 sales, solutions, and legal information ...................... 20 worldwide sales and design s upport ......... .............. 20 products .................................................................... 20 psoc? solutions ...................................................... 20 cypress developer community ................................. 20 technical support ................. .................................... 20
cy2308 document number: 38-07146 rev. *o page 3 of 20 pinouts figure 1. 16-pin soic pinout (top view) 9 16 fbk clka4 clka3 v dd gnd clkb4 clkb3 s1 1 2 3 4 5 6 7 8 10 11 12 13 14 15 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 pin definitions 16-pin soic pin signal description 1 ref [1] input reference frequency 2 clka1 [2] clock output, bank a 3 clka2 [2] clock output, bank a 4v dd power supply voltage 5 gnd power supply ground 6 clkb1 [2] clock output, bank b 7 clkb2 [2] clock output, bank b 8 s2 [3] select input, bit 2 9 s1 [3] select input, bit 1 10 clkb3 [2] clock output, bank b 11 clkb4 [2] clock output, bank b 12 gnd power supply ground 13 v dd power supply voltage 14 clka3 [2] clock output, bank a 15 clka4 [2] clock output, bank a 16 fbk pll feedback input select input decoding s2 s1 clock a1?a4 clock b1?b4 output source pll shutdown 00 tri-state tri-state pll y 0 1 driven tri-state pll n 10 driven [4] driven [4] reference y 1 1 driven driven pll n notes 1. weak pull down. 2. weak pull down on all outputs. 3. weak pull ups on these inputs. 4. outputs inverted and pll bypass mode for 2308-2 and 2308-3, s2 = 1 and s1 = 0.
cy2308 document number: 38-07146 rev. *o page 4 of 20 zero delay and skew control to close the feedback loop of the cy2308, the user has to connect any one of the eight available output pins to fbk pin. the output driving the fbk pin drives a total load of 7 pf plus any additional load that it drives. the relative loading of this output to the remaining outputs adjusts the input-output delay as shown in the figure 2 . for applications requiring zero input-output delay, all outputs including the one providing feedback is equally loaded. if input-output delay adjustm ents are required, use the zero delay and skew control graph to calculate loading differences between the feedback output and remaining outputs. for zero output-output skew, outputs are loaded equally. for further information on using cy2308, refer to the application note cy2308: zero delay buffer-an1234 . available cy2308 configurations device feedback from [5] bank a frequency bank b frequency cy2308-1 bank a or bank b reference reference cy2308-1h bank a or bank b reference reference cy2308-2 bank a reference reference / 2 cy2308-2 bank b 2 reference reference cy2308-3 bank a 2 reference reference [6] cy2308-3 bank b 4 reference 2 reference cy2308-4 bank a or bank b 2 reference 2 reference cy2308-5h bank a or bank b reference / 2 reference / 2 figure 2. ref. input to clka/clkb delay versus diff erence in loading between fbk pin and clka/clkb pins notes 5. user has to select one of the available outputs that drive th e feedback pin and need to connect selected output pin to fbk pi n externally. 6. output phase is indeterminant (0 or 180 from i nput clock). if phase integrity is required, use cy2308-2.
cy2308 document number: 38-07146 rev. *o page 5 of 20 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. supply voltage to ground potential ..............?0.5 v to +7.0 v dc input voltage (except ref) ........... ?0.5 v to v dd + 0.5 v dc input voltage ref .......................................?0.5 v to 7 v storage temperature ................................ ?65 c to +150 c junction temperature ................................................. 150 c static discharge voltage (mil-std-883, method 3015) .................................. >2000 v operating conditions for co mmercial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance, below 100 mhz ? 30 pf load capacitance, from 100 mhz to 133 mhz ? 15 pf c in input capacitance [7] ?7pf t pu power up time for all v dd ?s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics for commercial temperature devices parameter description test conditions min max unit v il input low voltage ? 0.8 v v ih input high voltage 2.0 ? v i il input low current v in = 0 v ? 50.0 ? a i ih input high current v in = v dd ? 100.0 ? a v ol output low voltage [8] i ol = 8 ma (-1, -2, -3, -4) i ol = 12 ma (-1h, -5h) ?0.4v v oh output high voltage [8] i oh = ?8 ma (-1, -2, -3, -4) i oh = ?12 ma (-1h, -5h) 2.4 ? v i dd (pd mode) power down supply current ref = 0 mhz ? 12.0 ? a i dd supply current unloaded outputs, 100 mhz ref, select inputs at v dd or gnd ?45.0ma ? 70.0 (-1h, -5h) ma unloaded outputs, 66 mhz ref (-1, -2, -3, -4) ? 32.0 ma unloaded outputs, 33 mhz ref (-1, -2, -3, -4) ? 18.0 ma notes 7. applies to both ref clock and fbk. 8. parameter is guaranteed by design and char acterization. not 100% tested in production.
cy2308 document number: 38-07146 rev. *o page 6 of 20 switching characteristics for commercial temperature devices parameter [9] description test conditions min typ max unit f in input frequency ? 10 ? 133.3 mhz t 1 output frequency 30 pf load 10 ? 100 (-1, -2, -3, -4) 66.67 (-5h) mhz t 1 output frequency 20 pf load, -1h, -5h devices 10 ? 133.3 (-1h) 66.67 (-5h) mhz t 1 output frequency 15 pf load, -1, -2, -3, -4 devices 10 ? 133.3 mhz t pd duty cycle [9] = t 2 ?? t 1 (-1, -2, -3, -4, -1h, -5h) measured at 1.4 v, f out = 66.66 mhz, 30 pf load 40.0 50.0 60.0 % t pd duty cycle [9] = t 2 ?? t 1 (-1, -2, -3, -4, -1h, -5h) measured at 1.4 v, f out < 50 mhz, 15 pf load 45.0 50.0 55.0 % t 3 rise time [9] (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 30 pf load ? ? 2.20 ns t 3 rise time [9] (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 15 pf load ? ? 1.50 ns t 3 rise time [9] (-1h, -5h) measured between 0.8 v and 2.0 v, 30 pf load ? ? 1.50 ns t 4 fall time [9] (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 30 pf load ? ? 2.20 ns t 4 fall time [9] (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 15 pf load ? ? 1.50 ns t 4 fall time [9] (-1h, -5h) measured between 0.8 v and 2.0 v, 30 pf load ? ? 1.25 ns t 5 output to output skew on same bank [9] (-1, -2, -3, -4) all outputs equally loaded ? ? 200 ps output to output skew (-1h, -5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-1, -4, -5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-2, -3) all outputs equally loaded ? ? 400 ps t 6 delay, ref rising edge to fbk rising edge [9] measured at v dd /2 ? 0 250 ps t 7 device to device skew [9] measured at v dd /2 on the fbk pins of devices ? 0 700 ps t 8 output slew rate [9] measured between 0.8 v and 2.0 v on -1h, -5h device using test circuit 2 1? ? v/ns t j cycle to cycle jitter [9] (-1, -1h, -4, -5h) measured at 66.67 mhz, loaded outputs, 15 pf load ?75 200 ps measured at 66.67 mhz, loaded outputs, 30 pf load ?? 200 ps measured at 133.3 mhz, loaded outputs, 15 pf load ?? 100 ps t j cycle to cycle jitter [9] (-2, -3) measured at 66.67 mhz, loaded outputs, 30 pf load ?? 400 ps measured at 66.67 mhz, loaded outputs, 15 pf load ?? 400 ps t lock pll lock time [9] stable power supply, valid clocks presented on ref and fbk pins ?? 1.0 ms note 9. all parameters are specified with loaded outputs.
cy2308 document number: 38-07146 rev. *o page 7 of 20 operating conditions for i ndustrial temper ature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) ?40 85 c c l load capacitance, below 100 mhz ? 30 pf load capacitance, from 100 mhz to 133 mhz ? 15 pf c in input capacitance [10] ?7pf t pu power up time for all v dds to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics for in dustrial temperature devices parameter description test conditions min max unit v il input low voltage ? 0.8 v v ih input high voltage 2.0 ? v i il input low current v in = 0 v ? 50.0 ? a i ih input high current v in = v dd ? 100.0 ? a v ol output low voltage [11, 12] i ol = 8 ma (-1, -2, -3, -4) i ol = 12 ma (-1h, -5h) ?0.4v v oh output high voltage [11, 12] i oh = ?8 ma (-1, -2, -3, -4) i oh = ?12 ma (-1h, -5h) 2.4 ? v i dd (pd mode) power down supply current ref = 0 mhz ? 25.0 ? a i dd supply current unloaded outputs, 100 mhz, select inputs at v dd or gnd ?45.0ma ?70 (-1h, -5h) ma unloaded outputs, 66 mhz ref (-1, -2, -3, -4) ? 35.0 ma unloaded outputs, 66 mhz ref (-1, -2, -3, -4) ? 20.0 ma notes 10. applies to both ref clock and fbk. 11. parameter is guaranteed by design and characterization. not 100% tested in production. 12. all parameters are specified with loaded outputs.
cy2308 document number: 38-07146 rev. *o page 8 of 20 switching characteristics for industrial temperature devices parameter [13] description test conditions min typ max unit f in input frequency ? 10 ? 133.3 mhz t 1 output frequency 30 pf load 10 ? 100 (-1, -2, -3, -4) 66.67 (-5h) mhz t 1 output frequency 20 pf load, -1h, -5h devices 10 ? 133.3 (-1h) 66.67 (-5h) mhz t 1 output frequency 15 pf load, -1, -2 , -3, -4 devices 10 ? 133.3 mhz t pd duty cycle [13, 14] = t 2 ?? t 1 (-1, -2, -3, -4, -1h, -5h) measured at 1.4 v, f out = 66.66 mhz, 30 pf load 40.0 50.0 60.0 % t pd duty cycle [13, 14] = t 2 ?? t 1 (-1, -2, -3, -4, -1h, -5h) measured at 1.4 v, f out < 50 mhz, 15 pf load 45.0 50.0 55.0 % t 3 rise time [13, 14] (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 30 pf load ? ? 2.50 ns t 3 rise time [13, 14] (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 15 pf load ? ? 1.50 ns t 3 rise time [13, 14] (-1h, -5h) measured between 0.8 v and 2.0 v, 30 pf load ? ? 1.50 ns t 4 fall time [13, 14] (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 30 pf load ? ? 2.50 ns t 4 fall time [13, 14] (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 15 pf load ? ? 1.50 ns t 4 fall time [13, 14] (-1h, -5h) measured between 0.8 v and 2.0 v, 30 pf load ? ? 1.25 ns t 5 output to output skew on same bank [13, 14] (-1, -2, -3, -4) all outputs equally loaded ? ? 200 ps output to output skew (-1h, -5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-1, -4, -5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-2, -3) all outputs equally loaded ? ? 400 ps t 6 delay, ref rising edge to fbk rising edge [13, 14] measured at v dd /2 ? 0 ? 250 ps t 7 device to device skew [13, 14] measured at v dd /2 on the fbk pins of devices ? 0 700 ps t 8 output slew rate [13, 14] measured between 0.8 v and 2.0 v on -1h, -5h device using test circuit 2 1 ? ? v/ns t j cycle to cycle jitter [13, 14] (-1, -1h, -4, -5h) measured at 66.67 mhz, loaded outputs, 15 pf load ? 75 200 ps measured at 66.67 mhz, loaded outputs, 30 pf load ? ? 200 ps measured at 133.3 mhz, loaded outputs, 15 pf load ? ? 100 ps t j cycle to cycle jitter [13, 14] (-2, -3) measured at 66.67 mhz, loaded outputs, 30 pf load ? ? 400 ps measured at 66.67 mhz, loaded outputs, 15 pf load ? ? 400 ps t lock pll lock time [13, 14] stable power supply, valid clocks presented on ref and fbk pins ? ? 1.0 ms notes 13. all parameters are specified with loaded outputs. 14. parameter is guaranteed by design and char acterization. not 100% tested in production.
cy2308 document number: 38-07146 rev. *o page 9 of 20 switching waveforms figure 3. duty cycle timing figure 4. all outputs rise/fall time figure 5. ou tput-output skew figure 6. input-output propagation delay figure 7. device-device skew t 1 t 2 1.4v 1.4v 1.4v output t 3 3.3v 0v 0.8v 2.0v 2.0v 0.8v t 4 1.4v t 5 output output 1.4v v dd /2 t 6 input fbk v dd /2 v dd /2 v dd /2 t 7 fbk, device 1 fbk, device 2
cy2308 document number: 38-07146 rev. *o page 10 of 20 typical duty cycle and i dd trends for cy2308-1, 2, 3, 4 [15, 16] duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz duty cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (for 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 10 0 12 0 14 0 02 468 number of loaded output s 33 m hz 66 m hz 100 m hz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 10 0 12 0 14 0 02468 number of loaded outputs 33 m hz 66 m hz 100 m hz notes 15. duty cycle is taken from ty pical chip measured at 1.4 v. 16. i dd data is calculated from i dd = i core + ncvf, where i core is the unloaded current. (n = number of outputs; c = capacitanc e load per output (f); v = voltage supply (v); f = frequency (hz).
cy2308 document number: 38-07146 rev. *o page 11 of 20 typical duty cycle and i dd trends for cy2308-1h, 5h [17, 18] duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (% ) 33 mhz 66 mhz 100 mhz duty cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (for 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 10 0 12 0 14 0 02 468 number of loaded outputs 33 mhz 66 mhz 100 mhz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 10 0 12 0 14 0 02468 number of loaded out put s 33 mhz 66 mhz 10 0 m h z notes 17. duty cycle is taken from ty pical chip measured at 1.4 v. 18. i dd data is calculated from i dd = i core + ncvf, where i core is the unloaded current. (n = number of outputs; c = capacitanc e load per output (f); v = voltage supply (v); f = frequency (hz).
cy2308 document number: 38-07146 rev. *o page 12 of 20 test circuits 0.1 ? f v dd 0.1 ? f v dd clk out c load outputs gnd gnd test circuit 1 v dd 0.1 ? f v dd clk out 10 pf outputs gnd gnd 1 k ? 1 k ? 0.1 ? f test circuit for t 8 , output slew rate on -1h, -5h device test circuit for all parameters except t 8 test circuit 2
cy2308 document number: 38-07146 rev. *o page 13 of 20 ordering information ordering code package type operating range cy2308si-1t [19] 16-pin soic ? tape and reel industrial cy2308zi-1h [19] 16-pin tssop industrial cy2308zi-1ht [19] 16-pin tssop ? tape and reel industrial cy2308si-2 [19] 16-pin soic industrial cy2308si-2t [19] 16-pin soic ? tape and reel industrial pb-free cy2308sxc-1 16-pin soic commercial cy2308sxc-1t 16-pin soic ? tape and reel commercial cy2308sxi-1 16-pin soic industrial cy2308sxi-1t 16-pin soic ? tape and reel industrial cy2308sxc-1h 16-pin soic commercial cy2308sxc-1ht 16-pin soic ? tape and reel commercial cy2308sxi-1h 16-pin soic industrial CY2308SXI-1HT 16-pin soic ? tape and reel industrial cy2308zxc-1h 16-pin tssop commercial cy2308zxc-1ht 16-pin tssop ? tape and reel commercial cy2308zxi-1h 16-pin tssop industrial cy2308zxi-1ht 16-pin tssop ? tape and reel industrial cy2308sxc-2 16-pin soic commercial cy2308sxc-2t 16-pin soic ? tape and reel commercial cy2308sxi-2 16-pin soic industrial cy2308sxi-2t 16-pin soic ? tape and reel industrial cy2308sxc-3 16-pin soic commercial cy2308sxc-3t 16-pin soic ? tape and reel commercial cy2308sxi-3 16-pin soic industrial cy2308sxi-3t 16-pin soic ? tape and reel industrial cy2308sxc-4 16-pin soic commercia cy2308sxc-4t 16-pin soic ? tape and reel commercial cy2308sxi-4 16-pin soic industrial cy2308sxi-4t 16-pin soic ? tape and reel industrial note 19. not recommended for new designs.
cy2308 document number: 38-07146 rev. *o page 14 of 20 ordering code definitions x = t or blank t = tape and reel; blank = tube dash or variant code temperature range: x = c or i c = commercial = 0 c to +70 c; i = industrial = ?40 c to +85 c x = pb-free, blank = leaded package type: x = s or z s = 16-pin soic, z = 16-pin tssop part identifier company id: cy = cypress 2308 cy x xx x - x
cy2308 document number: 38-07146 rev. *o page 15 of 20 package diagrams figure 8. 16-pin soic (150 mil) s16.15/sz16.15 package outline, 51-85068 figure 9. 16-pin tssop 4.40 mm body z16.173 package outline, 51-85091 51-85068 *e 51-85091 *d
cy2308 document number: 38-07146 rev. *o page 16 of 20 acronyms document conventions units of measure table 1. acronyms used in this document acronym description fbk feedback pll phase locked loop mux multiplexer table 2. units of measure symbol unit of measure symbol unit of measure c degrees celsius w microwatt db decibels ma milliampere fc femtocoulomb mm millimeter ff femtofarad ms millisecond hz hertz mv millivolt kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolt k ? kilohm ? ohm mhz megahertz pa picoampere m ? megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolt ? sigma: one standard deviation vrms microvolts root-mean-square
cy2308 document number: 38-07146 rev. *o page 17 of 20 errata this section describes the errors and workaround solution for cy press zero delay clock buffers belonging to the families cy2308 . details include errata trigger conditions, scope of impact and available workaround. contact your local cypress sales re presentative if you have questions. part numbers affected cy2308 errata summary cy2308 qualification status product status: in production qualification report la st updated on 11/27/2012 ( http://www.cypress.com/?rid=72595 ) part number device characteristics cy2308sxc-1 all variants cy2308sxc-1t all variants cy2308sxi-1 all variants cy2308sxi-1t all variants cy2308sxc-3 all variants cy2308sxc-3t all variants cy2308sxi-3 all variants cy2308sxi-3t all variants cy2308sxc-1h all variants cy2308sxc-1ht all variants cy2308sxi-1h all variants CY2308SXI-1HT all variants cy2308zi-1h all variants cy2308zi-1ht all variants cy2308zxc-1h all variants cy2308zxc-1ht all variants cy2308zxi-1h all variants cy2308zxi-1ht all variants cy2308zxi-1ht all variants items part number silicon revision fix status 1. start up lock time issue all b silicon fixed. new silicon available from ww 10 of 2013
cy2308 document number: 38-07146 rev. *o page 18 of 20 1. start up lock time issue problem definition output of cy2308 fails to locks within 1 ms (as per data sheet spec) parameters affected pll lock time trigger condition(s) start up scope of impact it can impact the performance of system and its throughput workaround apply reference input (refclk) before power up (v dd ) input noise propagates to output due to absence of reference input signal during power up. if reference input is present during power up , the noise will not propagate to output and device will start no rmally without problems. fix status this issue is due to design marginality. two minor design modifications have been made to address this problem. ? addition of vco bias detector block as shown in the following fi gure which keeps comparator powe r down till vco bias is present and thereby eliminating the prop agation of noise to feedback. ? bias generator enhancement for successful initialization.
cy2308 document number: 38-07146 rev. *o page 19 of 20 document history page document title: cy2308, 3.3 v zero delay buffer document number: 38-07146 rev. ecn orig. of change submission date description of change ** 110255 szv 12/17/01 changed from specif ication number: 38-00528 to 38-07146 *a 118722 rgl 10/31/02 added note 4. *b 121832 rbi 12/14/02 power up requirements added to operating conditions information *c 235854 rgl 06/24/04 added pb-free devices *d 310594 rgl 02/09/05 removed obsolete parts in the ordering information table specified typical value for cycle-to-cycle jitter *e 1344343 kvm / ved 08/20/07 brought the ordering info rmation table up to date: removed three obsolete parts and added two parts changed titles to tables that are specific to commercial and industrial temperature ranges *f 2568575 aesa 09/19/08 updated template. added note 19 ?not recommended for new designs.? changed idd (pd mode) from 12.0 to 25.0 ? a for commercial and industrial temperature devices deleted duty cycle parameters for f out < ? 50 mhz removed cy2308si-4, cy2308si-4t and cy2308sc-5ht. *g 2632364 kvm 01/08 /09 corrected tssop package size (f rom 150 mil to 4.4 mm) in ordering information table *h 2673353 kvm / pyrs 03/13/09 reverted i dd (pd mode) and duty cycle parameters back to the values in revision *e: changed i dd (pd mode) from 25 to 12 ? a for commercial temperature devices added duty cycle parameters for f out < ? 50 mhz for commercial and industrial devices. *i 2897373 cxq 03/22/10 updated ordering information . updated package diagrams . updated copyright section. *j 2971365 bash 07/06/10 updated input to output skew and power down current number in functional description, page 1 update pin descriptions in ?pin description? column, table1, page 2 added ?input frequency? parameter and output frequency for -1h and -5h in ?switching characteristics table? and removed footnote, page 4, 5, and 7. modified description on page 1 and page 3 to make clear that user has to select one of the outputs to drive feedback. added footnote in ?available cy2308 configurations? table, page 3, for clarification. *k 3047133 cxq 10/04/2010 sunset review. no chan ge to data sheet from last revision. *l 3055192 cxq 10/11/2010 updated ordering information (removed part cy2308sxi-5h and cy2308sxi-5hi). *m 3402187 bash 10/11/2011 updated ordering information (removed prune part numbers cy2308si-1h and cy2308si-1ht). updated package diagrams . updated in new template. *n 4128657 cinm 10/23/2013 updated package diagrams : spec 51-85068 ? changed revision from *d to *e. updated in new template. completing sunset review. *o 4307800 cinm 03/13/2014 added errata .
document number: 38-07146 rev. *o revised march 13, 2014 page 20 of 20 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2308 ? cypress semiconductor corporation, 2001-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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